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Sheet目录3872

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PIC16C5X

DS30453D-page 46

Preliminary

2002 Microchip Technology Inc.

9.2

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external com-

ponents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKIN pin. That means that the

WDT will run even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins have been stopped, for example,

by execution of a SLEEP instruction. During normal

operation or SLEEP, a WDT Reset or Wake-up Reset

generates a device RESET.

The TO bit (STATUS<4>) will be cleared upon a Watch-

dog Timer Reset (Section 6.3).

The WDT can be permanently disabled by program-

ming the configuration bit WDTE as a ’0’ (Section 9.1).

Refer to the PIC16C5X Programming Specifications

(Literature Number DS30190) to determine how to

access the configuration word.

9.2.1

WDT PERIOD

An 8-bit counter is available as a prescaler for the

Timer0 module (Section 8.2), or as a postscaler for the

Watchdog Timer (WDT), respectively. For simplicity,

this counter is being referred to as “prescaler” through-

out this data sheet. Note that the prescaler may be

used by either the Timer0 module or the WDT, but not

both. Thus, a prescaler assignment for the Timer0

module means that there is no prescaler for the WDT,

and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio (Section 6.4).

The WDT has a nominal time-out period of 18 ms (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by writ-

ing to the OPTION register. Thus, time-out a period of

a nominal 2.3 seconds can be realized. These periods

vary with temperature, VDD and part-to-part process

variations (see Device Characterization).

Under worst case conditions (VDD = Min., Temperature

= Max., WDT prescaler = 1:128), it may take several

seconds before a WDT time-out occurs.

9.2.2

WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the pres-

caler, if assigned to the WDT, and prevents it from tim-

ing out and generating a device RESET.

The SLEEP instruction RESETS the WDT and the pres-

caler, if assigned to the WDT. This gives the maximum

SLEEP time before a WDT Wake-up Reset.

FIGURE 9-1:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 9-1:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A

OPTION

—

Tosc

Tose

PSA

PS2

PS1

PS0

--11 1111 --11 1111

Legend: u = unchanged, - = unimplemented, read as '0'. Shaded cells not used by Watchdog Timer.

From TMR0 Clock Source

To TMR0

WDT Enable

EPROM Bit

PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Watchdog

Timer

Note:

T0CS, T0SE, PSA, PS2:PS0 are bits in the

OPTION register.

Prescaler

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